Design of an efficient aging aware reliable multiplier to reduce aging effects

Abstract

Digital multipliers are among the most critical arithmetic functional units. The Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed.. There are three types of multipliers Vedic multiplier base on Vedic arithmetic using Urdhva-Tiryabhyam sutra are proved to be the most efficient in terms of lower power consumption. overall performance of these systems depends on the throughput of the multiplier .A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. A multiplier is one of the chief hardware blocks in most digital and high concert systems such as microprocessors, digital signal processors. The CNFET-based multipliers have higher speed, and low power dissipation and it nearly reduces 99% PDP (power-delay product) as compared to the MOSFET In this paper, we propose an agingaware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers.