Design and implementation of carry select adder for 128 bit low power
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Abstract
Carry Select Adder is a prompt adder that is employed in processing of data processors for functioning quick arithmetic functions. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, the scope is to reduce the area of CSLA based on the efficient gate-level modification. In this paper 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed. To decrease area with insignificant speed penalty, set up a multiplexer basis add one circuit was projected. Based on this modification a new modified 32-Bit Square-root CSLA (SQRT CSLA) architecture has been developed. The modified architecture has been developed using Common Boolean Logic (CBL). The area of proposed design illustrates a decrease in support of 128-bit sizes which indicates attainment of method and not an easy trade-off of obstruction for area.
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