FPGA Based Efficient Implementation of Viterbi Decoder
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Abstract
Convolutional encoding is a forward error correction technique that is used for correction of errors at the receiver end. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In this paper, we present a Spartan XC3S400A Field- Programmable Gate Array efficient implementation of Viterbi Decoder with a constraint length of 3 and a code rate of 1/3. The proposed architecture can be realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2 using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into Xilinx Virtex-5, XC5VLX110T FPGA. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameters in today’s wireless technology. In this paper, a high speed feed forward viterbi decoder has been designed using track back architecture and embedded BRAM of target FPGA. It shows that the larger the constraint length used in a convolutional encoding process, the more powerful the code produced.
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