Square and Cube Architecture using Less Complex and Low Power Architectures

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Published: Dec 31, 2015
Keywords:
DWT, Radix8, Parallel Structure, VEDIC, Urdhva Tiryagbhyam, Anurupyena Sutra, Modified Booth

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BELLAM SREEKANYA
K.RAKESH

Abstract

In this paper we are going to explore the importance of the design of a Low power and less area square and cube architectures using Vedic sutra , the optimized multiplier are having regular, less complex and parallel structure in design thus this kind of algorithm and its designs used to design square and cube circuit using Vedic sutras over and over again times square and cube are the most sustained on operations in several digital signal processing applications and computation can be condensed using Radix8 and the overall processor performance can be improved for numerous applications.

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How to Cite
[1]
BELLAM SREEKANYA and K.RAKESH, “Square and Cube Architecture using Less Complex and Low Power Architectures”, Int. J. Comput. Eng. Res. Trends, vol. 2, no. 12, pp. 1232–1235, Dec. 2015.
Issue
Vol. 2 No. 12 (2015): December (2015) Issue
Section
Research Articles
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References

Y.Yu Fengqi and A. N.Willson,“Multirate digital squarer architectures,” in Proc. 8th IEEE Int. conf on Electronics, Circuits and Systems (ICECS 2001), Malta, Sept. 2–5, 2001

Swami Bharati Krisna Tirtha, “Vedic Mathematics,” Motilal Banarsidass Publishers, Delhi 1965

Performance analysis of multipliers for powerspeed trade-off in VLSI designs Sumit R. VaidyaD. R. Dandekar, ISSN: 1790-5117

Implementation of Multiplier using Vedic Algorithm. ISSN: 2278- 3075, Volume-2, Issue- 6, May 2013