Design and Simulation of High Speed Low Power CMOS Comparator
Main Article Content
Abstract
In high-speed high-resolution analog to digital converters, comparators have a key role in quality of performance. High power consumption and delay is one of the drawbacks of these circuits which can be reduced by using suitable architectures. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep submicron design technologies. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 0.8V DC supply voltage and 250 MHz clock frequency. The proposed circuit analyses the Inverter based differential amplifier design compared to double tail comparator is a less delay and controls the power dissipation. Finally output results shown by using T-Spice tool in TSMC018
Article Details
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
IJCERT Policy:
The published work presented in this paper is licensed under the Creative Commons Attribution 4.0 International (CC BY 4.0) license. This means that the content of this paper can be shared, copied, and redistributed in any medium or format, as long as the original author is properly attributed. Additionally, any derivative works based on this paper must also be licensed under the same terms. This licensing agreement allows for broad dissemination and use of the work while maintaining the author's rights and recognition.
By submitting this paper to IJCERT, the author(s) agree to these licensing terms and confirm that the work is original and does not infringe on any third-party copyright or intellectual property rights.
References
B. Goll and H. Zimmermann, “A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 810–814, Nov. 2009.
S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS,” Int. J. Analog Integer. Circuits Signal Process, vol. 66, no. 2, pp. 213–221, Feb. 2011.
A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, “Supply boosting technique for designing very lowvoltage mixed-signal circuits in standard CMOS,” in Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, Aug. 2010, pp. 893–896.
B. J. Blalock, “Body-driving as a Low-Voltage Analog Design Technique for CMOS technology,” in Proc. IEEE Southwest Symp. Mixed-Signal Design, Feb. 2000, pp. 113–118.
M. Maymandi- Nejad and M. Sachdev, “1-bit quantiser with rail to rail input range for sub-1V __ modulators,” IEEE Electron. Lett, vol. 39, no. 12, pp. 894– 895, Jan. 2003.
Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T.-S. Cheung, J. Ogawa, N. Tzartzanis, W. W. Walker, and T. Kuroda, “A 40Gb/s CMOS clocked comparator with bandwidth modulation technique,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1680– 1687, Aug. 2005.
B. Goll and H. Zimmermann, “A 0.12 μm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6 GHz,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 316–317.
B. Goll and H. Zimmermann, “A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 328–329.
B. Goll and H. Zimmermann, “Low-power 600MHz comparator for 0.5 V supply voltage in 0.12 μm CMOS,” IEEE Electron. Lett, vol. 43, no. 7, pp. 388–390, Mar. 2007.
D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps Setup Hold time,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 314–315.