Design of Low Power TPG with LP-LFSR
Main Article Content
Abstract
This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. The proposed test pattern generator reduces the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-O Red with the seed generated by the low power linear feedback shift register [LP-LFSR]. The proposed scheme is evaluated by using, a synchronous pipelined 4x4 and 8x8 Braun array multipliers. The System-On-Chip (SOC) approach is adopted for implementation on Altera Field Programmable Gate Arrays (FPGAs) based SOC kits with Nios soft-core processor. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.
Article Details
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
IJCERT Policy:
The published work presented in this paper is licensed under the Creative Commons Attribution 4.0 International (CC BY 4.0) license. This means that the content of this paper can be shared, copied, and redistributed in any medium or format, as long as the original author is properly attributed. Additionally, any derivative works based on this paper must also be licensed under the same terms. This licensing agreement allows for broad dissemination and use of the work while maintaining the author's rights and recognition.
By submitting this paper to IJCERT, the author(s) agree to these licensing terms and confirm that the work is original and does not infringe on any third-party copyright or intellectual property rights.
References
BalwinderSingh, Arunkhosla and SukhleenBindra "Power Optimization of linear feedback shift register(LFSR) for low power BIST" , 2009 IEEE international Advance computing conference(IACC 2009) Patiala,India 6-7 March 2009.
Y.Zorian, "A Distributed BIST control scheme for complex VLSI devices," Proc. VLSI Test Symp., P.4- 9,1993.
P.Girard," survey of low-power testing of VLSI circuits," IEEE design and test of computers, Vol. 19,no.3,PP 80-90,May-June 2002.
MechrdadNourani,"Low-transition test pattern generation for BIST- Based Applications", IEEE TRANSACTIONS ON COMPUTERS, Vol 57,No.3 ,March 2008.
BOYE and Tian-Wang Li," A novel BIST scheme for low power testing," 2010 IEEE.
R.S.Katti,X.Y.Ruan , and H.Khattri," MultipleOutput Low-Power Linear feedback shift register design," IEEE Trans.circuitsSyst.I,Vol.53,No.7,pp1487-1495,July 2006.
P.Girard, L.Guiller, C.Landrault, S.Pravossoudovitch,andH.J.Wunderlich," A modified clock scheme for a low power BIST test pattern generator," 19th IEEE proc. VLSI test Symp.,CA,pp-306- 311,Apr-May 2001.
S.Wang and S.K.Gupta," DS-LFSR: a BIST TPG for low switching activity," IEEE Trans.computer-aided design of Integrated circuits and systems, Vol. 21,No.7,pp.842-851,July 2002.
I.Voyiatzis,A.paschalis,D.Nikolos and C.Halatsis, "An efficient built-in self test method for robust path delay fault testing," Journal of electronic testing: Theory and applications Vol.8,No.2,pp-219-222,Apr1996.
S.C.Lei, J.Guo, L.Cao, Z.Ye.Liu, and X.M.Wang,"SACSR: A low power BIST method for sequential circuits,: Academic Journal of XI'AN jiaotong university(English Edition),Vol.20,no.3,pp.155- 159,2008.
R.H.He,X.W.Li and Y.Z.Gong," A scheme for low power BIST test pattern generator," micro electronics& computer,no.2,pp.36-39 Feb.2003.
S.C. Lei, X.Y.Hou ,Z.B.Shao and F.Liang," A class of SIC circuits: theory and application in BIST design," IEEE trans. circuits syst. II, vol.55,no.2,pp.161-165,Feb.2008.