Analog and Digital PLL with Single Ended Ring VCO for “Full Swing Symmetrical Even Phase Outputs”
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Abstract
The most versatile application of a phase locked loop (PLL) is clock generation and clock recovery in microprocessors, networking, wired and wireless communication system and frequency synthesizers. Voltage controlled oscillators (VCO) are the important and crucial building block in the PLL. This paper proposes a “Single Ended Type Ring VCO with a New Delay Cell” for Full Swing Symmetrical Even Phase outputs. To meet the requirements of high-quality performance in portable device systems at low cost, a ring VCO structures of numerous differential delay cells have been commonly implemented in recently developed VCO monolithic integrated chips (ICs). However, compared with ring VCOs of single-ended delay cells, implementing ring VCOs of differential delay cells typically require a larger area, greater power consumption and a tail current circuit. Therefore, determining a method for designing a “Single Ended Ring-type VCO” with a wide tuning range, a small layout area ((without a tail current circuit) and high Signal to Noise Ratio (SNR) is crucial. Therefore, the designed Ring VCO is placed in PLL and simulates the miscellaneous blocks of phase locked loop (PLL). In addition that the proposed VCO with a new delay cell achieved (16.6-33) MHz wide tuning range with full swing symmetrical even phase outputs, which yielded -174.28dbc/Hz phase noise at 1MHz, occupied small layout area with only 5 transistored delay cell and consumed less power approximated to 0.48Megawatts operated at only 1.2V supply voltage in TSMC 180nm deep submicron technology.
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