DRAM based on Self Controllable Voltage Level Technique for Leakage Power in VLSI
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Abstract
Today trend is circuit characterized by reliability, low power dissipation, low leakage current, low cost and there is required to reduce each of these. Increase of chip complexity is consistently higher for memory circuits. The salient features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and low leakage current, most of these have get give a better advantage. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Since there is no additional circuitry needed for power reduction in this circuit design technique, there is no additional circuitry needed for power reduction Here 3T DRAM is implementing with self controllable voltage level (svl) technique is for reducing leakage current in 0.12um technology. The simulation is done by using microwind 3.1 & dsch2 and gives the advantage of reducing the leakage current up to 57%.
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