Design and implementation of Vedic Multiplier with adaptive hold logic
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Abstract
In this paper we address the devise convention with the achievement of Vedic multiplier in spite of bypassing multiplier keeping in mind to improve the performance in terms of more speed and less power delay, with our existing design we have concentrated on completion of row and column by pass multiplier which consist of multi-level MUX's and also full adders for aging aware circuit. Since the additional usage of MUX results additional delay and power dissipation for existing design. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on Vertical and Crosswise structure of Ancient Indian Vedic Mathematics. It generates all partial products and their sum in one step the proposed Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using HDL designer and precision synthesis tool.
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References
N.Ravi, Dr.T.JayachandraPrasad ,Dr.T.SubbaRao,Y.Subbaiah (2011), ―A Novel Low Power, Low Area Array Multiplier Design for DSP Applications ,Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011).
TriptiSharma,Prof.B.P.Singh,K.G.Sharma,NehaArora ― High speed ,low power 8t full adder cell with 45%improvement in threshold loass problem .
ShivshankarMishra,V,Narendar,Dr.R.A.Mishra(2011), ― On the design of high performance CMOS 1 bit full adder circuits ,Proceedings published by International Journal of Computer Applications(ICVCI2011).
M.B. Damle, Dr. S. S. Limaye (2012), ―Low-power Full Adder array-based Multiplier with Domino Logic , International Journal of advanced Research in Computer Engineering & Technology,Vol.1,Issue 4,June 2012 ,ISSN:2278-1323
J. Selvakumar, VidhyacharanBhaskar(2011), ― A Low Power Multiplier Architecture Based OnBypassing Technique for Digital Filter .
Aditya Kumar Singh, Bishnu Prasad De, SantanuMaity (2012), ― Design and Comparison of Multipliers Using Different Logic Styles ,International Journal of Soft Computing and Engineering(IJSCE),Vol.2,ISSN 2231- 2307
Vishal D Jaiswal, SarojV.Bakale, SonalS.Bhopale(2012), ― Implementationandcomparitve analysis of low power adder circuit , International Journal of advanced Technology & Engineering Research(IJATER),Vol.2,ISSN 2250-3536.
Ahmed M.shams,andMagdyA.Bayoumi , ― A new full adder cell for low power applications .
A novel multiplexer based low power full adder.
KevianNavi,Mohammad Reza Saatchi,OmidDaei (2009), ―A high speed Hybrid full adder ,European Journal of Scientific Research,Vol.26No.1(2009),pp.22-26.
Reza FaghihMirzaee,MohammedHosseinMoaiyeri,KeivanNavi(2010), ― High Speed NP-CMOS and Multi Output Dynamic Full Adder Cells .
B.Sathiyabama,Dr.S.Malarkka (2012), ― Low power novel hybrid adders for datapath circuits in DSP processor ,Indian Journal of Computer Science and Engineering (IJCSE),Vol.3No.1 ,ISSN 0976-5166.
D. Mohapatra, G. Karakonstantis, and K. Roy, ―Low-power process variation tolerant arithmetic units using input-based elastic clocking, in Proc. ACM/IEEE ISLPED, Aug. 2007, pp. 74–79.
D. Baneres, J. Cortadella, and M. Kishinevsky, ―Variable-latency design by function speculation, in Proc. DATE, 2009, pp. 1704–1709.
Y. Lee and T. Kim, ―A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs, in Proc. ASPDAC, 2011, pp. 603–608.