Impact Factor:6.549
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International Journal
of Computer Engineering in Research Trends (IJCERT)
Scholarly, Peer-Reviewed, Open Access and Multidisciplinary
International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary
ISSN(Online):2349-7084 Submit Paper Check Paper Status Conference Proposal
[1+ ARM Ltd., San Jose, CA, “Embedded trace macrocellarchitecture specification,†2006. *2+ B. Tabara and K. Hashmi, “Transaction-level modeling and debug of SoCs,†presented at the IP SoC Conf., France, 2004 *3+ ARM Ltd., San Jose, CA, “AMBA Specification (REV 2.0) ARMIHI0011A,†1999. *4+ ARM Ltd., San Jose, CA, “ARM. AMBA AHB Trace Macrocell (HTM) technical reference manual ARM DDI 0328D,†2007. [5] J. Gaisler, E. Catovic, M. Isomaki, K. Glembo, and S. Habinc, “GRLIB IP core user’s manual, gaisler research,†2009. [6+ E. Rotenberg, S. Bennett, and J. E. Smith, “A trace cache microarchitecture and evaluation,†IEEE Trans. Comput., vol. 48, no. 1, pp. 111–120, Feb. 1999. [7] A. B. T. Hopkins and K. D. Mcdonald-Maier, “Debug support strategy for systems-on-chips with multiple processor cores,†IEEE Trans. Comput., vol. 55, no. 1, pp. 174–184, Feb. 2006. [8] B. Vermeulen, K. Goosen, R. van Steeden, and M. Bennebroek, “Communication-centric SoC debug using transactions,†in Proc. 12th IEEE Eur. Test Symp., May 20–24, 2007, pp. 69–76. [9] Y.-T. Lin, C.-C. Wang, and I.-J. Huang, “AMBA AHB bus protocol checker with efficient debugging mechanism,†in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 18–21, 2008, pp. 928–931
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