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of Computer Engineering in Research Trends (IJCERT)

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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary

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Performance of AHB Bus Tracer with Dynamic Multiresolution and Lossless Real Time Compression

VELLANKI SATHEESH BABU, B.N. SRINIVASA RAO, , ,
Affiliations
Pursuing M.Tech, VLSI DESIGN, Dept of ECE
Assistant Professor, Department of Electronics and Communication Engineering Avanthi Institute of Engineering and Technology, Visakhapatnam, Andhra Pradesh, India.
:NOT ASSIGNED


Abstract
In this paper we demonstrate the On-Chip bus SoC(system-on-chip) infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization. The past two decades of SoC evolution have seen an exponential increase in complexity. Today’s devices have multiple processing units, CPUs, GPUs, DSPs, DMAs, third-party IP blocks and custom logic. As if the hardware is not complicated enough, there will of course be substantial amounts of sophisticated software code running on the SoC hardware/software integration, and testing are made very much harder. The commercial consequences of problems in the development flow are potentially dire: since the debugging / analysis needs are adaptable: some designers need all signals at cycle-level, while some others only care about the transactions. For the latter case, tracing all signals at cycle-level wastes a lot of trace memory. Thus, there must be a way to capture traces at different abstraction levels based on the specific debugging/analysis need.


Citation
VELLANKI SATHEESH BABU,B.N. SRINIVASA RAO."Performance of AHB Bus Tracer with Dynamic Multiresolution and Lossless Real Time Compression". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1245-1250, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1280.pdf,


Keywords : SoC(system-on-chip), bus tracer, On-Chip, SoC debugging and analysis.

References
[1+ ARM Ltd., San Jose, CA, “Embedded trace
macrocellarchitecture specification,” 2006.
*2+ B. Tabara and K. Hashmi, “Transaction-level
modeling and debug of SoCs,” presented at the IP SoC
Conf., France, 2004
*3+ ARM Ltd., San Jose, CA, “AMBA Specification (REV
2.0) ARMIHI0011A,” 1999.
*4+ ARM Ltd., San Jose, CA, “ARM. AMBA AHB Trace
Macrocell (HTM) technical reference manual ARM DDI
0328D,” 2007.
[5] J. Gaisler, E. Catovic, M. Isomaki, K. Glembo, and S.
Habinc, “GRLIB IP core user’s manual, gaisler
research,” 2009.
[6+ E. Rotenberg, S. Bennett, and J. E. Smith, “A trace
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Comput., vol. 48, no. 1, pp. 111–120, Feb. 1999.
[7] A. B. T. Hopkins and K. D. Mcdonald-Maier,
“Debug support strategy for systems-on-chips with
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55, no. 1, pp. 174–184, Feb. 2006.
[8] B. Vermeulen, K. Goosen, R. van Steeden, and M.
Bennebroek, “Communication-centric SoC debug using
transactions,” in Proc. 12th IEEE Eur. Test Symp., May
20–24, 2007, pp. 69–76.
[9] Y.-T. Lin, C.-C. Wang, and I.-J. Huang, “AMBA
AHB bus protocol checker with efficient debugging
mechanism,” in Proc. IEEE Int. Symp. Circuits Syst.,
Seattle, WA, May 18–21, 2008, pp. 928–931


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DOI:10.22362/ijcert