Square and Cube Architecture using Less Complex and Low Power Architectures
BELLAM SREEKANYA, K.RAKESH, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Science for Women
In this paper we are going to explore the importance of the design of a Low power and less area square and
cube architectures using Vedic sutra , the optimized multiplier are having regular, less complex and parallel structure in
design thus this kind of algorithm and its designs used to design square and cube circuit using Vedic sutras over and
over again times square and cube are the most sustained on operations in several digital signal processing applications
and computation can be condensed using Radix8 and the overall processor performance can be improved for numerous
BELLAM SREEKANYA,K.RAKESH."Square and Cube Architecture using Less Complex and Low Power Architectures". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1232-1235 , December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1277.pdf,
 Y.Yu Fengqi and A. N.Willson,â€œMultirate digital
squarer architectures,â€ in Proc. 8th IEEE Int. conf on
Electronics, Circuits and Systems (ICECS 2001), Malta,
Sept. 2â€“5, 2001
 Swami Bharati Krisna Tirtha, â€œVedic
Mathematics,â€ Motilal Banarsidass Publishers, Delhi
 Performance analysis of multipliers for powerspeed trade-off in VLSI designs Sumit R. VaidyaD. R.
Dandekar, ISSN: 1790-5117
 Implementation of Multiplier using Vedic
Algorithm. ISSN: 2278- 3075, Volume-2, Issue- 6, May
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