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of Computer Engineering in Research Trends (IJCERT)

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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary

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Investigation on Performance of high speed CMOS Full adder Circuits

(M.Tech) VLSI, Dept. of ECE
Assistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Science for Women

- In this paper we demonstrate the performance analysis of CMOS Full adder circuits in this connection the full Adder is designed using CMOS logic style by dividing it in three modules so that it can be optimized at various levels. First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs simultaneously and have a good driving capability. The objective this concept is identified the comparison of power, surface area and complexity of Full adder designs using CMOS Logic Styles. Full adder Design is better compared to conventional design. Transistor Design with respect to power, delay, Power Delay Product Comparison. It is observed that less power is consumed in the Transmission based full adder than the Convention full adder and Pass Transistor full adder.

KATTUPALLI KALYANI,G.VASANTH RAO."Investigation on Performance of high speed CMOS Full adder Circuits ". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1228-1231, December - 2015, URL :,

Keywords : High speed, low power. CMOS logic style, full adder.

[1] N. Weste, and K. Eshranghian, “Principles of
CMOS VLSI Design: A System Perspective,” Reading
MA: Wesley, 1993.
[2] Sanjeev Kumar and Manoj Kumar “4-2
Compressor design with New XOR-XNOR Module”,
4th International Conference on Advanced Computing
and Communication technologies, pp. 106-111, 2014.
[3] Meher, P.; Mahapatra, K.K. "Low power noise
tolerant domino 1-bit full adder", International
Conference on Advances in Energy Conversion
Technologies (ICAECT), pp. 125 – 129, 2014
[4] Vojin G. Oklobdzija, “Simple and Efficient Circuit
for Fast VLSI Adder Realization,” IEEE International
Symposium on Circuits and Systems Proceedings,
1988, pp. 1-4.
[5] J.Rabaey, “Digital Integrated Circuits: A Design
Prospective,” Prentice- Hall, Englewood Cliffs, NJ,
[6] R. Zimmermann and W. Fichtner, “Low-power
logic styles: CMOS versus pass-transistor logic,” IEEE
Journal of Solid–State Circuits, vol.32, pp.1079-1090,
July 1997.
[8] Devi, Padma, Ashima Girdher, and Balwinder
Singh. "Improved carry select adder with reduced
area and low power consumption." International
Journal of Computer Applications 3.4 (2010): 14-18.
[9] D. Radhakrishnan, “Low-voltage low-power
CMOS full adder,” IEEE Proc. Circuits Devices Syst.,
vol. 148, no. 1, pp. 19–24, Feb. 2001.


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