Programmable reversible logic is gain wide consideration as a logic design style for modern nanotechnology and quantum computing with minimal impact on circuit heat generation in improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Then, a novel 3*3 programmable UPG gate capable of calculating the universal logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, a novel 4*4 reversible programmable RC gate capable of nine unique logical calculations at low cost and delay is presented and verified. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. These designs are compared to previously existing designs, and their advantages in terms of cost and delay are analyzed.Then, the RMUX is used to improve a reversible SRAM cell we previously presented. The memory cell and comparator are implemented in the design of a Min/Max Comparator device.

KONDADASULA VEDA NAGA SAI SRI,M.SAI RAMA KRISHNA."Circuit for Revisable Quantum Multiplier Implementation of Adders with Reversible Logic". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1216-1221, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1274.pdf,

[1] C. Bennett, "Logical Reversibility of Computation,"
IBM Journal of Research and Development, vol. 17,
1973, pp. 525-532.
[2] E. Fredkin and T. Toffoli, "Conservative Logic,"
International Journal of Theoretical Physics, vol. 21,
1980, pp. 219-53.
[3] T. Toffoli, "Reversible Computing," Technical Report
MIT/LCS/TM- 151, 1980.
[4] A. Peres, “Reversible Logic and Quantum
Computers,” Physical Review, vol. 32, iss. 6, 1985, pp.
3266-3267.
[5] A. N. Al-Rabadi, “Closed-system quantum logic
network implementation of the viterbi algorithm,”
Facta universitatis-Ser.: Elec. Energy., vol. 22, no. 1, pp.
1–33, April 2009.
[6] H. Thapliyal, N. Ranganathan, and R. Ferreira,
"Design of a Comparator Tree Based on Reversible
Logic," 10th Proceedings of the IEEE International
Conference on Nanotechnology, 2010, pp 1113-6.
[7] M. Morrison, M. Lewandowski, R. Meana and N.
Ranganathan, "Design of Static and Dynamic RAM
Arrays Using a Novel Reversible LogicGate and
Decoder," IEEE NANO, Aug. 2011.
[8] M. Morrison, M. Lewandowski, R. Meana and N.
Ranganathan, "Design of a Novel Reversible ALU with
Enhanced Carry Look-Ahead Adder," IEEE NANO,
Aug. 2011.
[9] N. Weste and D. Harris, CMOS VLSI Design: A
Circuits and Systems Perspective, 3 ed., Boston:
Addison Wesley, 2005, pp. 715-738.
[10] J. Smolin and D. Divincenzo, "Five Two-bit
Quantum Gates Are Sufficient to Implement the
Quantum Fredkin Gate," Physical Review A, vol. 53,
1996, pp 2855-6
[11] H. Thapliyal and N. Ranganathan, "Design of
Efficient Reversible Binary Subtractors Based on A New
Reversible Gate," Proc. of the IEEE Computer Society
Annual Symposium on VLSI, 2009, pp 229-234.
[12] M. Morrison and N. Ranganathan, "Design of a
Reversible ALU Based on Novel Programmable
Reversible Logic Gate Structures," ISVLSI, Jul. 2011, pp.
126-131.
[13] D. Deustch, "Quantum Computational Networks,"
Proceedings of the Royal Society of London. Series A,
Mathematical and Physical Sciences, vol. 425, iss. 1868,
1989, pp. 73-90
[14] R. Feynman, "Simulating Physics with
Computers," International Journal of Theoretical
Physics, 1982.
[15] R. Feynman, "Quantum Mechanical Computers,"
Foundations of Physics, vol. 16, iss. 6, 1986