Circuit for Revisable Quantum Multiplier Implementation of Adders with Reversible Logic
KONDADASULA VEDA NAGA SAI SRI, M.SAI RAMA KRISHNA, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Science For Women
Programmable reversible logic is gain wide consideration as a logic design style for modern nanotechnology
and quantum computing with minimal impact on circuit heat generation in improved computer architecture and arithmetic
logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to
the previous Swap gate is presented. Then, a novel 3*3 programmable UPG gate capable of calculating the universal logic
calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then
implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX
gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing
Fredkin gate is presented and verified. Next, a novel 4*4 reversible programmable RC gate capable of nine unique logical
calculations at low cost and delay is presented and verified. The UPG and RC are implemented in the design of novel
sequential and tree-based comparators. These designs are compared to previously existing designs, and their advantages
in terms of cost and delay are analyzed.Then, the RMUX is used to improve a reversible SRAM cell we previously
presented. The memory cell and comparator are implemented in the design of a Min/Max Comparator device.
KONDADASULA VEDA NAGA SAI SRI,M.SAI RAMA KRISHNA."Circuit for Revisable Quantum Multiplier Implementation of Adders with Reversible Logic". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1216-1221, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1274.pdf,
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