FPGA Based Efficient Implementation of Viterbi Decoder
BEERAM RAJ MOHAN REDDY, BELLAM VARALAKSHMI, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
Convolutional encoding is a forward error correction technique that is used for correction of errors at the
receiver end. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In
this paper, we present a Spartan XC3S400A Field- Programmable Gate Array efficient implementation of Viterbi Decoder
with a constraint length of 3 and a code rate of 1/3. The proposed architecture can be realized by an Adaptive Viterbi
Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2 using Verilog HDL. Simulation is done using Xilinx
ISE 12.4i design software and it is targeted into Xilinx Virtex-5, XC5VLX110T FPGA. The parameters of Viterbi algorithm
can be changed to suit a specific application. The high speed and small area are two important design parameters in
todayâ€™s wireless technology. In this paper, a high speed feed forward viterbi decoder has been designed using track back
architecture and embedded BRAM of target FPGA. It shows that the larger the constraint length used in a convolutional
encoding process, the more powerful the code produced.
BEERAM RAJ MOHAN REDDY,BELLAM VARALAKSHMI."FPGA Based Efficient Implementation of Viterbi Decoder". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1076-1082, December- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1246.pdf,
 Altera Corporation. Apex II data sheet, 2001.V http://www.altera.com.
 Annapolis Microsystems, Inc. WILD-ONE Reference Manual, 1999.
 W. Burleson, R. Tessier, D. Goeckel, S.Swaminathan, P. Jain, J. Euh, S. Venkatraman, and V. Thyagarajan. Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations for Improved Performance and Reduced Power. In IEEE Conference on Acoustics, Speech, and Signal Processing, May 2001.
 F. Chan and D. Haccoun. Adaptive Viterbi Decoding of Convolutional Codes over Memoryless Channels IEEETransactions on Communications, 45(11):1389â€“ 1400, Nov. 1997.
 M. Kivioja, J. Isoaho, and L. Vanska. Design and Implementation of a Viterbi Decoder with FPGAs. Journal of VLSI Signal Processing, 21(1):5â€“14, May 1999.
 C. F. Lin and J. B. Anderson. M-algorithm Decoding of Channel Convolutional Codes. In Proceedings, Princeton Conference of Information Science and Systems, pages 362â€“366, Princeton, NJ, Mar. 1986.
 A. Michelson and A. Levesque. Error-control Techniques for Digital Communication. John Wiley and Sons, New York, NY,1985.
 B. Pandita and S. K. Roy. Design and Implementation of a Viterbi Decoder Using FPGAs. In Proceedings, IEEE International Conference on VLSI Design, pages 611â€“614, Jan. 1999.
 J. Proakis. Digital Communications. McGraw-Hill, New York, NY, 1995.
 H. Schmit and D. Thomas. Hidden Markov Modelling and Fuzzy Controllers in FPGAs. In Proceedings, IEEE Workshop on FPGA-based Custom Computing Machines, pages 214â€“221,Napa, Ca, Apr. 1995.
 S. J. Simmons. Breath-first Trellis Decoding with Adaptive Effort. IEEE Transactions on Communications, 38:3â€“12, Jan. 1990.
 S. Swaminathan. An FPGA-based Adaptive Viterbi Decoder. Masterâ€™s thesis, University of Massachusetts, Amherst, Department of Electrical and Computer Engineering, 2001.
 R. Tessier and W. Burleson. Reconfigurable Computing and Digital Signal Processing: A Survey. Journal of VLSI Signal Processing, 28(1):7â€“27, May 2001.
 Texas Instruments, Inc. TMS320C6201 DSP Data Sheet, 2001.
 Xilinx Corporation. Virtex II data sheet, 2001. http://www.xilinx.com.
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