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Design of an efficient aging aware reliable multiplier to reduce aging effects

(M.Tech) VLSI, Dept. of ECE
Associate Professor, Dept. of ECE Priyadarshini Institute of Technology & Management

Digital multipliers are among the most critical arithmetic functional units. The Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed.. There are three types of multipliers Vedic multiplier base on Vedic arithmetic using Urdhva-Tiryabhyam sutra are proved to be the most efficient in terms of lower power consumption. overall performance of these systems depends on the throughput of the multiplier .A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. A multiplier is one of the chief hardware blocks in most digital and high concert systems such as microprocessors, digital signal processors. The CNFET-based multipliers have higher speed, and low power dissipation and it nearly reduces 99% PDP (power-delay product) as compared to the MOSFET In this paper, we propose an agingaware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers

BANDANADHAM BALA KRANTHI KUMAR,AL.SHABNA SAMANTHA TERA."Design of an efficient aging aware reliable multiplier to reduce aging effects". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1070-1075 , December- 2015, URL :,

Keywords : Adaptive Hold Logic(AHL), variable Latency, Reliable Multiplier, Positive Bias Temperature Instability(PBTI),Negative Bias Temperature Instability(PBTI)

[1] Y. Cao. (2013). Predictive Technology Model (PTM) and NBTI Model 
[2] S. Zafar et al., “A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates,” in Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2006, pp. 23–25. 
[3] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold voltage instabilities in high-k gate dielectric stacks,” IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 45–64, Mar. 2005. 
[4] H.-I. Yang, S.-C.Yang, W. Hwang, and C.-T. Chuang, “Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM,” IEEE Trans. Circuit Syst., vol. 58, no. 6, pp. 1239–1251, Jun. 2011. 
[5] R. Vattikonda, W. Wang, and Y. Cao, “Modeling and miimization of pMOS NBTI effect for robust naometer design,” in Proc. ACM/IEEE DAC, Jun. 2004, pp. 1047–1052. 
[6] H. Abrishami, S. Hatami, B. Amelifard, and M. Pedram, “NBTI-aware flip-flop characterization and design,” in Proc. 44th ACM GLSVLSI, 2008, pp. 29–34 
[7] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “NBTI-aware synthesis of digital circuits,” in Proc. ACM/IEEE DAC, Jun.2007, pp. 370–375. 
[8] A. Calimera, E. Macii, and M. Poncino, “Design techniqures for NBTI-tolerant power-gating architecture,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 59, no. 4, pp. 249–253, Apr. 2012. 
[9] K.-C. Wu and D. Marculescu, “Joint logic restructuring and pin reorder-ing against NBTIinduced performance degradation,” in Proc. DATE, 2009, pp. 75–80. 
[10] Y. Lee and T. Kim, “A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs,” in Proc. ASP- DAC, 2011, pp. 603–608. 
[11]M. Basoglu, M. Orshansky, and M. Erez, “NBTIaware DVFS: A new approach to saving energy and increasing processor lifetime,” in Proc. ACM/IEEE ISLPED, Aug. 2010, pp. 253–258. 
[12] K.-C. Wu and D. Marculescu, “Aging-aware timing analysis and optimization considering path sensitization,” in Proc. DATE, 2011, pp. 1–6. 
[13] K. Du, P. Varman, and K. Mohanram, “High performance reliable variable latency carry select addition,” in Proc. DATE, 2012, pp. 1257–1262. 
[14] A. K. Verma, P. Brisk, and P. Ienne, “Variable latency speculative addition: A new paradigm for arithmetic circuit design,” in Proc. DATE, 2008, pp. 1250–1255. 
[15] D. Baneres, J. Cortadella, and M. Kishinevsky, “Variable-latency design by function speculation,” in Proc. DATE, 2009, pp. 1704–1709.


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