Design and implementation of high speed 8 bit Vedic multiplier on FPGA
ANNAM ARAVIND KUMAR, SK. MASTAN BASHA, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
In high speed digital signal processing units arithmetic logic units, multiplier and accumulate units, the
multipliers are use as the key block. A systems performance is generally determined by the speed of the multiplier since
multiplier is one of the key hardware component in high performance systems such as FIR filters, digital signal processors
and microprocessors etc. Vedic Mathematics is the ancient system of mathematics which has a unique technique of
calculations based on 16 Sutras. With the increasing constraints on delay, more and more emphasis is being laid on
design of faster multiplications. The Array multiplier, Vedic 4*4 multiplier and 8*8 multiplier are designed, then 16*16
multiplier. These adders are called compressors. Amongst these Vedic multipliers based on Vedic mathematics are
presently under focus due to these being one of the fastest and low power multiplier. In this paper a 4 X 4 Vedic
multiplier is designed using reversible logic gates which is efficient in terms of constant inputs, garbage outputs, quantum
cost, area, speed and power. The design is simulated using Verilog. Compressor based Vedic Multipliers show
considerable improvements in speed and area efficiency over the conventional ones.
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