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IJCERT Journal ISSN(Online):2349-7084

International Journal
of Computer Engineering in Research Trends (IJCERT)

Scholarly, Peer-Reviewed, Open Access and Multidisciplinary


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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary

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A Novel Architecture for Matching the Data Protected With an Error-Correcting Code (ECC)

Sk.Parvin Bhano, T.Vineela, , ,
Affiliations
(M.Tech) –VLSI & ES, Dept of ECE, Vasireddy Venkatadri Institute of Technology (VVIT),
Assistant Professor, Dept of ECE, Vasireddy Venkatadri Institute of Technology (VVIT), Nambur (V), Guntur(Dt),Andhra Pradesh, India.
:NOT ASSIGNED


Abstract
In this paper we presented a novel architecture for matching the data protected with an Error-Correcting Code (ECC) which proposed to reduce latency and complexity where Data comparison is widely used in computing system to perform so many operations. Where incoming information is needs to be compared with a piece of stored data to locate the matching entry. If both incoming bits and stored bits are matching means there is no error if mismatched means some type of error will occur like random error or burst error. To detect and correct the error here error correcting codes are used. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance and also demonstrates LDPC coding and decoding for Error Correcting Codes further more examines whether the incoming data matches the stored data if a certain number of burst errors are corrected.


Citation
Sk.Parvin Bhano,T.Vineela."A Novel Architecture for Matching the Data Protected With an Error-Correcting Code (ECC)". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.849-855, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1207.pdf,


Keywords : Low Power and Low Complexity in Chip, Systematic Error Correcting Code

References
[1] Byeong Yong Kong, Jihyuck Jo, Hyewon Jeong, Mina Hwang,Soyoung Cha, Bongjin Kim, and InCheol Park “Low-Complexity Low-Latency Architecture for Matching Of Data EncodedWith Hard Systematic ErrorCorrecting Codes” IEEE transactions on (vlsi) systems, vol. 22, no. 7, July 2014 
[2] J. D. Warnock, Y.-H. Chan, S. M. Carey, H. Wen, P. J. Meaney, G. Gerwig and W. V. Huott “Circuit and physical design implementation of the microprocessor chip for the Enterprise system,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 151– 163, Jan. 2012. 
[3].W. Wu, D. Somasekhar, and S.-L. Lu, “Direct compare of information coded with error-correcting codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 11, pp. 2147– 2151, Nov. 2012. 
[4].S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2004.
 [5] Y. Lee, H. Yoo, and I.-C. Park, “6.4Gb/s multithreaded BCH encoder and decoder for multichannel SSD controllers,” in ISSCC Dig. Tech. Papers, 2012, pp. 426–427 .
[6] M. Tremblay and S. Chaudhry, “A thirdgeneration 65nm 16-core 32-thread plus 32- scoutthread CMT SPARC processor,” in ISSCC. Dig. Tech. Papers, Feb. 2008, pp. 82–83. 
[7] H. Ando, Y. Yoshida, A. Inoue, I. Sugiyama, T. Asakawa, K. Morita, T. Muta, and T. Motokurumada, S. Okada, H. Yamashita, and Y. Satsukawa, “A 1.3 GHz fifth generation SPARC64 microprocessor,” in IEEE ISSCC. Dig. Tech. Papers, Feb. 2003, pp. 246–247


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DOI:10.22362/ijcert