A Novel Architecture for Matching the Data Protected With an Error-Correcting Code (ECC)
Sk.Parvin Bhano, T.Vineela, , ,
Affiliations (M.Tech) –VLSI & ES, Dept of ECE, Vasireddy Venkatadri Institute of Technology (VVIT),Assistant Professor, Dept of ECE, Vasireddy Venkatadri Institute of Technology (VVIT), Nambur (V), Guntur(Dt),Andhra Pradesh, India.
In this paper we presented a novel architecture for matching the data protected with an Error-Correcting
Code (ECC) which proposed to reduce latency and complexity where Data comparison is widely used in computing
system to perform so many operations. Where incoming information is needs to be compared with a piece of stored
data to locate the matching entry. If both incoming bits and stored bits are matching means there is no error if
mismatched means some type of error will occur like random error or burst error. To detect and correct the error here
error correcting codes are used. To further reduce the latency and complexity, in addition, a new butterfly-formed
weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance and also demonstrates
LDPC coding and decoding for Error Correcting Codes further more examines whether the incoming data matches the
stored data if a certain number of burst errors are corrected.
Sk.Parvin Bhano,T.Vineela."A Novel Architecture for Matching the Data Protected With an Error-Correcting Code (ECC)". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.849-855, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1207.pdf,
Keywords : Low Power and Low Complexity in Chip, Systematic Error Correcting Code
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