Impact Factor:6.549
 Scopus Suggested Journal: Tracking ID for this title suggestion is: 55EC484EE39417F0

International Journal
of Computer Engineering in Research Trends (IJCERT)

Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

Welcome to IJCERT

International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

ISSN(Online):2349-7084                 Submit Paper    Check Paper Status    Conference Proposal

Back to Current Issues

Novel Design of Low Power Comparator Using Reversible Gates

(M.Tech) VLSI, Dept. of ECE
Assistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Science For Women

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. This paper presents a novel design of reversible comparator using the existing reversible gates and proposed new Reversible BJN gate. All the comparators have been modeled and verified using VHDL and ModelSim. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

IMMADISETTY SIVA PARVATHI,G.VASANTH RAO."Novel Design of Low Power Comparator Using Reversible Gates". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.887-892, November- 2015, URL :,

Keywords : Advanced computing, Modified Toffoli gate, Reversible arithmetic unit, Reversible logic circuits.

[1] R. Landauer, ‚Irreversibility and Heat Generation in the Computational Process‛, IBM Journal of Research and Development, 5, pp. 183- 191, 1961. 
[2] R. Landauer, ‚Irreversibility and Heat Generation in the Computational Process,‛ IBM Journal of Research and Development, Vol. 5, No. 3, 1961, pp. 183-191. 
[3] G. E. Moore, ‚Cramming More Components onto Integrated Circuits,‛ Electronics, Vol. 38, No. 8, 1965.
[4] C. H. Bennett, ‚Logical Reversibility of Computation,‛ IBM Journal of Research and Development, Vol. 17, 1973, 
[5] M. Mohammadi and M. Eshghi, ‚On Figureures of Merit in Reversible and Quantum Logic Designs,‛ Quantum Information Processing, Vol. 8, No. 4, 2009, pp. 297-318. 
[6] D. Maslov and G. W. Dueck, ‚Improved Quantum Cost for n-Bit Toffoli Gates,‛ IEEE Electronics Letters, Vol.39, No. 25, 2003, pp. 1790-1791. 
[7] V. Vedral, A. Bareno and A. Ekert, ‚Quantum Networks for Elementary Arithmetic Operations,‛ 1995. 
[8] R. Feynman, ‚Quantum Mechanical Computers,‛ Optic News, Vol. 11, 1985, pp. 11-20. 
[9] T. Toffoli, ‚Reversible Computing,‛ Tech memo MIT/ LCS/TM-151, MIT Lab for Comp. Sci, 1980. [10] E. Fredkin and T. Toffoli, ‚Conservative Logic,‛ International Journal of Theoretical Physics, Vol. 21 
[11] H. G. Rangaraju, V. Hegde, K. B. Raja and K. N. Muralidhara, ‚Design of Efficient Reversible Binary Comparator,‛International Conference on Communication Technology and System Design, 7-9 December 2011. 
[12] M. H. Azad Khan Md., ‚Design of Full Adder with Reversible Gate,‛ International Conference on Computer and Information Technology, Dhaka, 27-28 December 2002, pp. 515-519. 
[13] H. R. Bhagyalakshmi and M. K. Venkatesha, ‚Design of a Multifunction BVMF Reversible Logic Gate and Its Applications,‛ International Journal of Computer Applications 
[14] H. Thapliyal and N. Ranganathan, ‚A New Design of the Reversible Subtractor Circuit,‛ 2011 11th IEEE International Conference on Nanotechnology, Portland Marriott, 
[15] B. Dehghan, ‚Survey the Inverse Property of Quantum Gates for Concurrent Error Detection,‛ Journal of Basic and Applied Scientific Research, 2013, pp. 603-608.


Download :

Refbacks : Currently there are no Refbacks

Support Us

We have kept IJCERT is a free peer-reviewed scientific journal to endorse conservation. We have not put up a paywall to readers, and we do not charge for publishing. But running a monthly journal costs is a lot. While we do have some associates, we still need support to keep the journal flourishing. If our readers help fund it, our future will be more secure.

Quick Links


Science Central

Score: 13.30

Submit your paper to