Novel Design of Low Power Comparator Using Reversible Gates
IMMADISETTY SIVA PARVATHI, G.VASANTH RAO, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Science For Women
Reversible logic has shown potential to have extensive applications in emerging technologies such as
quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. The
classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible
sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates.
Minimizing the number of garbage is very noticeable. This paper presents a novel design of reversible comparator using
the existing reversible gates and proposed new Reversible BJN gate. All the comparators have been modeled and verified
using VHDL and ModelSim. A comparative result is presented in terms of number of gates, number of garbage outputs,
number of constant inputs and Quantum cost. The design is useful for the future computing techniques like quantum
computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.
IMMADISETTY SIVA PARVATHI,G.VASANTH RAO."Novel Design of Low Power Comparator Using Reversible Gates". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.887-892, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1136.pdf,
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