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International Journal
of Computer Engineering in Research Trends (IJCERT)
Scholarly, Peer-Reviewed, Open Access and Multidisciplinary
International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary
ISSN(Online):2349-7084 Submit Paper Check Paper Status Conference Proposal
[1] R. Landauer, “Irreversibility and Heat Generation in the Computational Processâ€, IBM Journal of Research and Development, 5, pp. 183-191, 1961. [2] Prashanth.N.G, Savitha.A.P, M.B.Anandaraju, Nuthan.A.C Design and Synthesis of Fault Tolerant Full Adder/Subtractor Using Reversible Logic Gates (IJERA) Vol. 3, Issue 4, Jul-Aug 2013. [3] Adders Md. Saiful Islam, Muhammad Mahbubur Rahman, Zerina begum, and Mohd. Zulfiquar Hafiz. Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip [4] Ko-ChiKuon, Chi-WenChou Low power and high speed multiplier design with row by passing and parallel architecture, Microelectronics Journal41 (2010). [5] Yvav van Rentergem and Alexis De Vos Optimal Design of a Reversible Full Adder. 17 December 2004. [6] Manjeet Singh Sankhwar , Rajesh Khatri Int Design of High Speed Low Power Reversible Logic Adder Using HNG Gate. Journal of Engineering Research and Applications Vol. 4, Issue 1 January 2014. [7] Md.Belayet Alli,Md.samlur Rahman,Thmina Parvin ,optimized design of carry skip BCD adder using new FHNG Reversible logic gates (IJCS) july 2012. [8] P. Moallema, M. Ehsanpour ,A Novel Design of Reversible Multiplier Circuit June 2013. [9] Himanshu Thapliyal and M.B Srinivas, Novel Reversible Multiplier Architecture Using Reversible TSG Gate. [10] Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas,Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. [11] Md. Saiful Islam, A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology. [12] J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, and X. Li. Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. [13] Parisa Safari , Majid Haghparast , Asgar Azari,A Design of Fault Tolerant Reversible Arithmetic Logic Unit,Life Science Journal 2012. [14] Stephen Brown, Zvonko Vranesic, et al.†Fundamentals of Digital Logic with Verilog Design†The McGraw-Hill Companies, Second Edition. [15] H. Thapliyal and N. Ranganathan, "Design of Efficient Reversible Binary Subtractions Based on New Reversible Gate," Proc. of the I Computer Society Annual Symposium on VLSI, 2009
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