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of Computer Engineering in Research Trends (IJCERT)

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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary

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IMPLEMENTATION OF HARDWARE IP ROUTER BASED ON VLSI

K RAMA SUBBA RAO, SK. MASTAN BASHA, , ,
Affiliations
(M.Tech) VLSI, Dept. of ECE
Assitant Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
:NOT ASSIGNED


Abstract
A Network-on-chip is a new paradigm in complex system-on-chip designs that provide efficient on chip communication networks. It allows scalable communication and allows decoupling of communication and computation. The data is routed through the networks in terms of packets. We attempts to overcome latency and time reduction issue and can provide multipurpose networking router by means of verilog and it was synthesized in Xilinx 13.2 version, simulated Modelsim 10.0 version. In this paper our attempt is to provide a multipurpose networking router by means of Verilog code, by this we can maintain the same switching speed with more secured way of approach we have even the packet storage buffer on chip being generated by code in our design in the so we call this as the self-independent router called as the VLSI Based router. The three architectures were analyzed for their performance in terms of delay, throughput and latency and we concluded that CDMA router performs better than the other two.


Citation
K RAMA SUBBA RAO,SK. MASTAN BASHA."IMPLEMENTATION OF HARDWARE IP ROUTER BASED ON VLSI". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.841-846, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1128.pdf,


Keywords : Fictional Coverage, assertions, Randomization, Network-On-Chip,, Register blocks.

References
[1]Channamallikarjuna Mattihalli, Suprith Ron,Naveen Kolla ” VLSI Based Robust Router Architecture” Third International Conference on Intelligent Systems Modelling and Simulation,2012. 
[2]Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, Kaile Gao, and Bin Liang” Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes” ieee transactions on very large scale integration (vlsi) systems, vol. 21, no. 4, april 2013. 
[3]James Aweya “IP Router Architectures: An Overview”.
 [4]M. SOWMYA C. SHIREESHA G. SWETHA PRAKASH J. PATIL” VLSI Based Robust Router Architecture” .
 [5] M. Waldvogel, G. Varghese, J. Turner, and B. Plattner, “Scalable High Speed IP Routing Lookup,” Proc. ACM SIGCOMM’97, Cannes, France, Sept. 1997. 
[6] V. Srinivasan and G. Varghese, “Faster IP Lookups using Controlled Prefix Expansion,” Proc. ACM SIGMETRICS, May 1998. 
[7] S. Nilsson and G. Karlsson, “Fast Address Look-Up for Internet Routers,” Proc. Of IEEE Broadband Communications’98, April 1998. 
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[9]M. Thottethodi, A. R. Lebeck, and S. S. Mukherjee, "BLAM: ahigh performance routing algorithm for virtual cut-through networks," in Proceedings of the International Parallel and Distributed Processing Symposium 
[10] L. S. Peh and W. J. Dally, "A delay model and speculative architecture for pipelined routers," in Proceedings of the 7thInternational Symposium on High Performance Computer Architecture (HPCA). 
[11] A. V. Yakovlev, A. M. Koelmans, and L. Lavagno, "High-level modeling and design of asynchronous interface logic," IEEEDesign & Test of Computers.
 [12] H. Jingcao and R. Marculescu, "Energy- and performance aware mapping for regular NoC architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, pp. 551-562, 2005.
 [13] W. Hangsheng, L. S. Peh, and S. Malik, "A technology-aware and energy oriented topology exploration for on-chip Networks," in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition . 
[14] J. Duato, "A new theory of deadlock-free adaptive routing in wormhole networks," IEEE Transactions on Parallel and Distributed Systems, vol. 4. 
[15] S. Arjun, W. J. Dally, A. K. Gupta, and B. Towles, "GOAL: aload-balanced adaptive routing algorithm for torus networks," in Proceedings of the International Symposium on ComputerArchitecture.


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Citations Indices All
Citations 1026
h-index 14
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DOI:10.22362/ijcert