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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary
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[1]Channamallikarjuna Mattihalli, Suprith Ron,Naveen Kolla †VLSI Based Robust Router Architecture†Third International Conference on Intelligent Systems Modelling and Simulation,2012. [2]Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, Kaile Gao, and Bin Liang†Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes†ieee transactions on very large scale integration (vlsi) systems, vol. 21, no. 4, april 2013. [3]James Aweya “IP Router Architectures: An Overviewâ€. [4]M. SOWMYA C. SHIREESHA G. SWETHA PRAKASH J. PATIL†VLSI Based Robust Router Architecture†. [5] M. Waldvogel, G. Varghese, J. Turner, and B. Plattner, “Scalable High Speed IP Routing Lookup,†Proc. ACM SIGCOMM’97, Cannes, France, Sept. 1997. [6] V. Srinivasan and G. Varghese, “Faster IP Lookups using Controlled Prefix Expansion,†Proc. ACM SIGMETRICS, May 1998. [7] S. Nilsson and G. Karlsson, “Fast Address Look-Up for Internet Routers,†Proc. Of IEEE Broadband Communications’98, April 1998. [8]E. Filippi, V. Innocenti, and V. Vercellone, “Address Lookup Solutions for Gigabit Switch/Router,†Proc. Globecom’98, Sydney, Australia, Nov. 1998. [9]M. Thottethodi, A. R. Lebeck, and S. S. Mukherjee, "BLAM: ahigh performance routing algorithm for virtual cut-through networks," in Proceedings of the International Parallel and Distributed Processing Symposium [10] L. S. Peh and W. J. Dally, "A delay model and speculative architecture for pipelined routers," in Proceedings of the 7thInternational Symposium on High Performance Computer Architecture (HPCA). [11] A. V. Yakovlev, A. M. Koelmans, and L. Lavagno, "High-level modeling and design of asynchronous interface logic," IEEEDesign & Test of Computers. [12] H. Jingcao and R. Marculescu, "Energy- and performance aware mapping for regular NoC architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, pp. 551-562, 2005. [13] W. Hangsheng, L. S. Peh, and S. Malik, "A technology-aware and energy oriented topology exploration for on-chip Networks," in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition . [14] J. Duato, "A new theory of deadlock-free adaptive routing in wormhole networks," IEEE Transactions on Parallel and Distributed Systems, vol. 4. [15] S. Arjun, W. J. Dally, A. K. Gupta, and B. Towles, "GOAL: aload-balanced adaptive routing algorithm for torus networks," in Proceedings of the International Symposium on ComputerArchitecture.
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