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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

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Design and implementation of carry select adder for 128 bit low power

(M.Tech) VLSI, Dept. of ECE
Associate Professor, Dept. of ECE Priyadarshini Institute of Technology & Management

Carry Select Adder is a prompt adder that is employed in processing of data processors for functioning quick arithmetic functions. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, the scope is to reduce the area of CSLA based on the efficient gate-level modification. In this paper 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed. To decrease area with insignificant speed penalty, set up a multiplexer basis add one circuit was projected. Based on this modification a new modified 32-Bit Square-root CSLA (SQRT CSLA) architecture has been developed. The modified architecture has been developed using Common Boolean Logic (CBL). The area of proposed design illustrates a decrease in support of 128-bit sizes which indicates attainment of method and not an easy trade-off of obstruction for area.

DOMA ANISHA RANI,AL.SHABNA SAMANTHA TERA."Design and implementation of carry select adder for 128 bit low power". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.835-840, November- 2015, URL :,

Keywords : Area efficient, Square-root CSLA (SQRT CSLA), Common Boolean Logic (CBL), Binary to Excess-1 CONVERTER (BEC).

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