[1] Y. He, C. H. Chang, and J. Gu, "An area efficient 64- Bit square Root carry-select adder for low powerApplications, " in Proc. IEEE Int. Symp.Circuits Syst.,vol. 4, pp. 4082-4085, 2005. 
[2] P. Sreenivasulu, K. Srinivasa rao, Malla Reddy and A. Vinay Babu, “Energy and area efficient carry select adder on a reconfigurable hardwware”, International Journal of Engineering Research and Applicaions, vol. 2, Issue. 2, pp. 436-440, Mar 2012.
[3] “Enhanced Area Efficient Architecture for 128 bit Modified CSLA”, R.Priya, J.Senthil Kumar, 2013 
[4] I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin and Chien-Chang Peng, “An area efficient carry select adder design by sharing the common boolean logic term”, Proceedings on the International Multiconference of Engineering and computer scientist, IMECS 2012 
[5] Padma Devi, Ashima Girdher and Balwinder Singh"Improved Carry Select Adder with Reduced Areaand Low Power Consumption, " International Journalof Computer Applications, Vo1.3, No.4, pp. 14- 18,1998. 
[6]Edison A. J and C. S. Manikanda babu, “An efficient CSLA architecture for VLSI hardware implementation”, Interanational Journal for Mechanical and Industrial Engineering, vol. 2, Issue 5, 2012 
[7] B. Ramkumar, H.M. Kittur, and P. M. Karman, "ASICimplementation of modified faster carry save adder, "Eur. J. Sci. Res., vol. 42, no. 1, pp.53-58, 2010 
[8] He, Y. Chang, C. H. and Gu, J. "An Area Efficient 64- Bit Square Root Carry-Select Adder For Low PowerApplications, " in Proc. IEEE Int. Symp. Circuits Syst.,Vol.4, pp. 4082-4085, 2005 
[9]B. Ramkumar and Harish M Kittur, “Low power and area efficient carry select adder”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb 2012. 
[10] J. M. Rabaey, Digital Integrated Circuits-A Design Perspective, Upper Saddle River, NJ: Prentice-Hall, 2001 
[11]R. Priya and J. Senthilkumar, “Implementation and comparision of effective area efficient architecuture for CSLA”, Proceedings of IEEE InternationalConference on Emerging trends in Computing, Communicaton and Nano Technology, pp. 287-292, 2013 
[12] An Efficient Csla Architecture For Vlsi Hardware Implementation Edison A.J, Mr. C.S.Manikanda Babu, 2012 
[13] Akhilesh Tyagi, "A Reduced-Area Scheme for CarrySelectAdders," IEEE Transactions on Computers,Vo1.42, No.1 0, pp.1l63-1170, 1993. 
[14]B. Ramkumar , Harish M Kittur and P. M. Kannan, “ASIC implementation of modified faster carry save adder”, Eur. J. Sci. Res. , vol. 42, no. 1, pp. 53-58, Jun 2010. 
[15] “An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic, Ms. S.Manjui, Mr. V. Sornagopae, 2013