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of Computer Engineering in Research Trends (IJCERT)

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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary

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Design and Simulation of High Speed Low Power CMOS Comparator

A.Rajeswari, T.Venkatarao, , ,
Affiliations
(M.Tech) DECS Branch, Department of ECE
Asst.Professor, Department of ECE Vignan's Nirula Iinstitute of Technology & Science for Women Pedapalakaluru, Guntur, Andhra Pradesh, India
:NOT ASSIGNED


Abstract
In high-speed high-resolution analog to digital converters, comparators have a key role in quality of performance. High power consumption and delay is one of the drawbacks of these circuits which can be reduced by using suitable architectures. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep submicron design technologies. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 0.8V DC supply voltage and 250 MHz clock frequency. The proposed circuit analyses the Inverter based differential amplifier design compared to double tail comparator is a less delay and controls the power dissipation. Finally output results shown by using T-Spice tool in TSMC018


Citation
A.Rajeswari,T.Venkatarao."Design and Simulation of High Speed Low Power CMOS Comparator". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.699-704, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1101.pdf,


Keywords : CMOS comparator, low power, High Speed, Analog-to-Digital Converter and Tanner EDA tool

References
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[2] S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS,” Int. J. Analog Integer. Circuits Signal Process, vol. 66, no. 2, pp. 213–221, Feb. 2011. 
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[5] M. Maymandi- Nejad and M. Sachdev, “1-bit quantiser with rail to rail input range for sub-1V __ modulators,” IEEE Electron. Lett, vol. 39, no. 12, pp. 894– 895, Jan. 2003. 
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 [7] B. Goll and H. Zimmermann, “A 0.12 μm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6 GHz,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 316–317. 
[8] B. Goll and H. Zimmermann, “A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 328–329.
 [9] B. Goll and H. Zimmermann, “Low-power 600MHz comparator for 0.5 V supply voltage in 0.12 μm CMOS,” IEEE Electron. Lett, vol. 43, no. 7, pp. 388–390, Mar. 2007. 
[10] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps Setup Hold time,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 314–315.


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DOI:10.22362/ijcert