International Journal of Computer Engineering in Research Trends

Back to Current Issues

Area Efficient and High Speed Vedic Multiplier Using Different Compressors

RAJARAPU KRISHNANJANEYULU, Y.KONDAIAH, , ,

Affiliations
(M.Tech) VLSI, Dept. of ECE
Associate Professor, Dept. of ECE Priyadarshini Institute of Technology & Management

:NOT ASSIGNED

Abstract

The performance of trending technology in VLSI field supports ongoing expectation for high speed Processing and lower area consumption. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. The proposed design has reduced area, LUT tables and increase the speeds compared with the regular compressor based multiplier. The multiplication sutra between these 16 sutras is the Urdhva Tiryakbhayam sutra which means vertical and crosswise. In this paper it is used for designing a high speed, low power 4*4 multiplier. The proposed system is design using VHDL and it is implemented through Xilinx ISE 14.2. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.

Citation

RAJARAPU KRISHNANJANEYULU,Y.KONDAIAH."Area Efficient and High Speed Vedic Multiplier Using Different Compressors". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 10,pp.875-880, October- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1016.pdf,

Keywords : Ripple Carry Adder, half adder, full adder, Compressors, high speed multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.

References

[1] L. Ciminiera and A. Valenzano, "Low cost serial multipliers for high speed specialized processors," Computers and Digital Techniques, IEE Proc. E, vol. 135.5, 1988, pp. 259-265. 
[2] A.D.Booth, â€œA Signed Binary Multiplication Technique,â€ J. mech. And appl. math, vol 4, no.2, pp. 236-240, Oxford University Press, 1951.  
[3] C. R. Baugh, B. A. Wooley, â€œA Twoâ€™s Complement Parallel Array Multiplication Algorithm,â€, IEEE Trans. Computers 22(12), pp. 1045â€“1047, 1973. 
[4] Koren Israel, â€Computer Arithmetic Algorithms,â€ 2nd Ed, pp. 141-149, Universities Press, 2001. 
[5] L. Sriraman, T.N. Prabakar, â€œDesign and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics,â€ 1st Int. Conf. on Recent Advances in Information Technology, Dhanbad, India, 2012, IEEE Proc., pp. 782-787.
 [6] M. Ramalatha, K. Deena Dayalan, S. Deborah Priya, â€œHigh Speed Energy Efficient ALU Design using Vedic Multiplication Techniques,â€ Advances in Computational Tools for Engineering Applications, 2009, IEEE Proc., pp 600-603.
 [7] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, â€œVedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda,â€ pp. 5-45, Motilal Banarasidas Publishers, Delhi, 2009.
 [8] Himanshu Thapliyal and M. B. Srinivas, â€œAn efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics,â€ 48th IEEE Int. Midwest Symp. on Circuits and Systems, 2005, vol. 1, pp. 826-828. 
[9] Tiwari, Honey Durga, et al., "Multiplier design based on ancient Indian Vedic Mathematics, " Int. SoC Design Conf., 2008, vol. 2. IEEE Proc., pp. II-65 - II-68. 
[10] Hsiao, Shen-Fu, Ming-Roun Jiang, and Jia-Sien Yeh, "Design of highspeed low-power 3-2 counter and 4-2 compressor for fast multipliers,â€ IEEE Electronics Letters, vol. 34, no.4, pp. 341-343, Feb. 1998. 
[11] D. Radhakrishnan and A. P. Preethy, "Low power CMOS pass logic 4-2 compressor for high-speed multiplication," Circuits and Systems, Proc. 43rd IEEE Midwest Symp., vol. 3, pp. 1296-1298, 2000.

DOI Link : NOT ASSIGNED

Download :

V2I1016.pdf

Refbacks : Currently there are no Refbacks

Announcements

Authors are not required to pay any article-processing charges (APC) for their article to be published open access in Journal IJCERT. No charge is involved in any stage of the publication process, from administrating peer review to copy editing and hosting the final article on dedicated servers. This is free for all authors.

News & Events

Latest issue :Volume 10 Issue 1 Articles In press

A plagiarism check will be implemented for all the articles using world-renowned software. Turnitin.

Digital Object Identifier will be assigned for all the articles being published in the Journal from September 2016 issue, i.e. Volume 3, Issue 9, 2016.

IJCERT is a member of the prestigious.Each of the IJCERT articles has its unique DOI reference.
DOI Prefix : 10.22362/ijcert

IJCERT is member of The Publishers International Linking Association, Inc. (“PILA”)

Emerging Sources Citation Index (in process)

IJCERT title is under evaluation by Scopus.

Key Dates

☞ INVITING SUBMISSIONS FOR THE NEXT ISSUE :

☞ LAST DATE OF SUBMISSION : 31st March 2023

☞ SUBMISSION TO FIRST DECISION : In 7 Days

☞ FINAL DECISION : IN 3 WEEKS FROM THE DAY OF SUBMISSION

Important Announcements

All the authors, conference coordinators, conveners, and guest editors kindly check their articles' originality before submitting them to IJCERT. If any material is found to be duplicate submission or sent to other journals when the content is in the process with IJCERT, fabricated data, cut and paste (plagiarized), at any stage of processing of material, IJCERT is bound to take the following actions.
1. Rejection of the article.
2. The author will be blocked for future communication with IJCERT if duplicate articles are submitted.
3. A letter regarding this will be posted to the Principal/Director of the Institution where the study was conducted.
4. A List of blacklisted authors will be shared among the Chief Editors of other prestigious Journals
We have been screening articles for plagiarism with a world-renowned tool: Turnitin However, it is only rejected if found plagiarized. This more stern action is being taken because of the illegal behavior of a handful of authors who have been involved in ethical misconduct. The Screening and making a decision on such articles costs colossal time and resources for the journal. It directly delays the process of genuine materials.

Citation Index

Citations Indices	All
Citations	1026
h-index	14
i10-index	20
Source: Google Scholar

Acceptance Rate (By Year)

Acceptance Rate (By Year)
Year	Rate
2021	10.8%
2020	13.6%
2019	15.9%
2018	14.5%
2017	16.6%
2016	15.8%
2015	18.2%
2014	20.6%

 Conference Proposal

 Peer Review

 Digital Library

 Register here

 Conference Proposal

 Special Issue Proposal

 Conference Proposal Guidelines

 Upcoming Conference

DOI:10.22362/ijcert

Welcome to IJCERT