Impact Factor:6.549
 Scopus Suggested Journal: Tracking ID for this title suggestion is: 55EC484EE39417F0

International Journal
of Computer Engineering in Research Trends (IJCERT)

Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

Welcome to IJCERT

International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

ISSN(Online):2349-7084                 Submit Paper    Check Paper Status    Conference Proposal

Back to Current Issues

Area Efficient and High Speed Vedic Multiplier Using Different Compressors

(M.Tech) VLSI, Dept. of ECE
Associate Professor, Dept. of ECE Priyadarshini Institute of Technology & Management

The performance of trending technology in VLSI field supports ongoing expectation for high speed Processing and lower area consumption. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. The proposed design has reduced area, LUT tables and increase the speeds compared with the regular compressor based multiplier. The multiplication sutra between these 16 sutras is the Urdhva Tiryakbhayam sutra which means vertical and crosswise. In this paper it is used for designing a high speed, low power 4*4 multiplier. The proposed system is design using VHDL and it is implemented through Xilinx ISE 14.2. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.

RAJARAPU KRISHNANJANEYULU,Y.KONDAIAH."Area Efficient and High Speed Vedic Multiplier Using Different Compressors". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 10,pp.875-880, October- 2015, URL :,

Keywords : Ripple Carry Adder, half adder, full adder, Compressors, high speed multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.

[1] L. Ciminiera and A. Valenzano, "Low cost serial multipliers for high speed specialized processors," Computers and Digital Techniques, IEE Proc. E, vol. 135.5, 1988, pp. 259-265. 
[2] A.D.Booth, “A Signed Binary Multiplication Technique,” J. mech. And appl. math, vol 4, no.2, pp. 236-240, Oxford University Press, 1951.  
[3] C. R. Baugh, B. A. Wooley, “A Two’s Complement Parallel Array Multiplication Algorithm,”, IEEE Trans. Computers 22(12), pp. 1045–1047, 1973. 
[4] Koren Israel, ”Computer Arithmetic Algorithms,” 2nd Ed, pp. 141-149, Universities Press, 2001. 
[5] L. Sriraman, T.N. Prabakar, “Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics,” 1st Int. Conf. on Recent Advances in Information Technology, Dhanbad, India, 2012, IEEE Proc., pp. 782-787.
 [6] M. Ramalatha, K. Deena Dayalan, S. Deborah Priya, “High Speed Energy Efficient ALU Design using Vedic Multiplication Techniques,” Advances in Computational Tools for Engineering Applications, 2009, IEEE Proc., pp 600-603.
 [7] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, “Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda,” pp. 5-45, Motilal Banarasidas Publishers, Delhi, 2009.
 [8] Himanshu Thapliyal and M. B. Srinivas, “An efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics,” 48th IEEE Int. Midwest Symp. on Circuits and Systems, 2005, vol. 1, pp. 826-828. 
[9] Tiwari, Honey Durga, et al., "Multiplier design based on ancient Indian Vedic Mathematics, " Int. SoC Design Conf., 2008, vol. 2. IEEE Proc., pp. II-65 - II-68. 
[10] Hsiao, Shen-Fu, Ming-Roun Jiang, and Jia-Sien Yeh, "Design of highspeed low-power 3-2 counter and 4-2 compressor for fast multipliers,” IEEE Electronics Letters, vol. 34, no.4, pp. 341-343, Feb. 1998. 
[11] D. Radhakrishnan and A. P. Preethy, "Low power CMOS pass logic 4-2 compressor for high-speed multiplication," Circuits and Systems, Proc. 43rd IEEE Midwest Symp., vol. 3, pp. 1296-1298, 2000.


Download :

Refbacks : Currently there are no Refbacks

Support Us

We have kept IJCERT is a free peer-reviewed scientific journal to endorse conservation. We have not put up a paywall to readers, and we do not charge for publishing. But running a monthly journal costs is a lot. While we do have some associates, we still need support to keep the journal flourishing. If our readers help fund it, our future will be more secure.

Quick Links


Science Central

Score: 13.30

Submit your paper to