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Implementation of a Fast Sign Detection Algoritm for the RNS Moduli Set {2N+1 -1, 2N -1, 2N }, N = 16, 64

GARNEPUDI SONY PRIYANKA, K.V.K.V.L. PAVAN KUMAR, , ,

Affiliations
(M.Tech) DECS Branch, Department of ECE
Asst.Professor, Department of ECE Vignan's Nirula Iinstitute of Technology & Science for Women Pedapalakaluru, Guntur, Andhra Pradesh, India

:NOT ASSIGNED

Abstract

- In this dissertation a fast sign detection algorithm for the residue number system (RNS) moduli set {2N+1 -1, 2N -1 , 2N }, N =16,64 is illustrated. This algorithm allows parallel implementation and completes the implementation with simply modulo 2n additions. This unit can be implemented using one carry save adder, one comparator, one carry generation unit and post processing unit. The results of this algorithm confirm that the area and delay are reduced compared to mixed radix conversion and Chinese reminder theroms. This algorithm is implemented using verilog language tool in Xilinx 13.2 version.

Citation

GARNEPUDI SONY PRIYANKA,K.V.K.V.L. PAVAN KUMAR."Implementation of a Fast Sign Detection Algoritm for the RNS Moduli Set {2N+1 -1, 2N -1, 2N }, N = 16, 64". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 10,pp.674-678, OCTOBER - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1004.pdf,

Keywords : residue number system (RNS), restricted moduli set, sign detection.

References

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[7] P. Mohan, “RNS-to-binary converter for a new three-moduli set {2n+1-1, 2n, 2n-1},” IEEE Trans. Cir-

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