Design and implementation of Vedic Multiplier with adaptive hold logic
A.Pravallika , Dr.K.Gouthami, , ,
Affiliations Department of ECE Vignan's Nirula Iinstitute of Technology & Science for Women Pedapalakaluru, Guntur, Andhra Pradesh, India
In this paper we address the devise convention with the achievement of Vedic multiplier in spite of bypassing multiplier keeping in mind to improve the performance in terms of more speed and less power delay, with our existing design we have
concentrated on completion of row and column by pass multiplier which consist of multi-level MUX's and also full adders for aging
aware circuit. Since the additional usage of MUX results additional delay and power dissipation for existing design. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on Vertical and Crosswise structure of
Ancient Indian Vedic Mathematics. It generates all partial products and their sum in one step the proposed Vedic multiplier is coded
in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using HDL designer
and precision synthesis tool.
A.Pravallika ,Dr.K.Gouthami."Design and implementation of Vedic Multiplier with adaptive hold logic". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 10,pp.663-668, OCTOBER - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1002.pdf,
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