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IJCERT Journal ISSN(Online):2349-7084

International Journal
of Computer Engineering in Research Trends (IJCERT)

Scholarly, Peer-Reviewed, Open Access and Multidisciplinary


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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary

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Design and implementation of Vedic Multiplier with adaptive hold logic

A.Pravallika , Dr.K.Gouthami, , ,
Affiliations
Department of ECE Vignan's Nirula Iinstitute of Technology & Science for Women Pedapalakaluru, Guntur, Andhra Pradesh, India
:NOT ASSIGNED


Abstract
In this paper we address the devise convention with the achievement of Vedic multiplier in spite of bypassing multiplier keeping in mind to improve the performance in terms of more speed and less power delay, with our existing design we have concentrated on completion of row and column by pass multiplier which consist of multi-level MUX's and also full adders for aging aware circuit. Since the additional usage of MUX results additional delay and power dissipation for existing design. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on Vertical and Crosswise structure of Ancient Indian Vedic Mathematics. It generates all partial products and their sum in one step the proposed Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using HDL designer and precision synthesis tool.


Citation
A.Pravallika ,Dr.K.Gouthami."Design and implementation of Vedic Multiplier with adaptive hold logic". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 10,pp.663-668, OCTOBER - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1002.pdf,


Keywords : Ripple Carry (RC) Adder, Multiplication, Vedic Mathematics, Vedic Multiplier (VM), Urdhava Tiryakbhyam Sutra.

References
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[2] TriptiSharma,Prof.B.P.Singh,K.G.Sharma,NehaArora ― High speed ,low power 8t full adder cell with 45%improvement in threshold loass problem‖. 
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[4] M.B. Damle, Dr. S. S. Limaye (2012), ―Low-power Full Adder array-based Multiplier with Domino Logic‖, International Journal of advanced Research in Computer Engineering & Technology,Vol.1,Issue 4,June 2012 ,ISSN:2278-1323 
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[10] KevianNavi,Mohammad Reza Saatchi,OmidDaei (2009), ―A high speed Hybrid full adder‖,European Journal of Scientific Research,Vol.26No.1(2009),pp.22-26. 
[11] Reza FaghihMirzaee,MohammedHosseinMoaiyeri,KeivanNavi(2010), ― High Speed NP-CMOS and Multi Output Dynamic Full Adder Cells‖. 
[12] B.Sathiyabama,Dr.S.Malarkka (2012), ― Low power novel hybrid adders for datapath circuits in DSP processor‖,Indian Journal of Computer Science and Engineering (IJCSE),Vol.3No.1 ,ISSN 0976-5166. 
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Citations Indices All
Citations 1026
h-index 14
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DOI:10.22362/ijcert