Design of DC-DC Boost Converter in CMOS 0.18Âµm Technology
M.RAMA DEVI, R.SUNIL KUMAR, M.MADHAVA KUMAR, ,
Affiliations Gayatri Vidya Parishad College of Engineering for Women, Visakhapatnam, Andhra Pradesh, India.
A CMOS DC-DC boost converter with fastest settling time and less quiescent current with a feedback control is implemented. An extra path is introduced because of an error amplifier (OTA) which has an effective control for fast response. Efficient compensation with soft-start is used to make the quiescent current low. An on-chip current sensing circuit is introduced with less number of I/O pins for current mode control. In this project, the DC-DC boost converter is designed in Cadence virtuoso 0.18Âµm technology with a 5V supply. With a wide range of loads, it provides 25V at the output, 50mA load current with 90% efficiency. The circuit is operated at 500 KHz clock frequency with output ripple voltage of 20mV by using 4.7ÂµF off-chip capacitor and 75ÂµH off-chip inductor.
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