1.
BEERAM RAJ MOHAN REDDY, BELLAM VARALAKSHMI. FPGA Based Efficient Implementation of Viterbi Decoder. Int. J. Comput. Eng. Res. Trends [Internet]. 2015 Dec. 31 [cited 2026 Aug. 14];2(12):1076-82. Available from: https://www.ijcert.org/index.php/ijcert/article/view/519