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SUNKARA YAMUNA RANI, BELLAM VARALAKSHMI. Implementation of Double Precision Floating Point Multiplier in VHDL. Int. J. Comput. Eng. Res. Trends [Internet]. 2015 Oct. 31 [cited 2026 Jun. 10];2(10):881-8. Available from: https://www.ijcert.org/index.php/ijcert/article/view/256