ANNAM ARAVIND KUMAR; SK. MASTAN BASHA. Design and implementation of high speed 8 bit Vedic multiplier on FPGA. International Journal of Computer Engineering in Research Trends, [S. l.], v. 2, n. 12, p. 1062–1069, 2015. Disponível em: https://www.ijcert.org/index.php/ijcert/article/view/521. Acesso em: 17 jun. 2026.