CHADARASUPALLI NAGA LAKSHMI; P T BALAKRISHNA. ASIC Design of Reversible Full Adder and Multiplier Circuits. International Journal of Computer Engineering in Research Trends, [S. l.], v. 2, n. 11, p. 882–886, 2015. Disponível em: https://www.ijcert.org/index.php/ijcert/article/view/295. Acesso em: 22 jul. 2026.