SUNKARA YAMUNA RANI; BELLAM VARALAKSHMI. Implementation of Double Precision Floating Point Multiplier in VHDL. International Journal of Computer Engineering in Research Trends, [S. l.], v. 2, n. 10, p. 881–888, 2015. Disponível em: https://www.ijcert.org/index.php/ijcert/article/view/256. Acesso em: 10 jun. 2026.